An advanced technique for making the highly integrated semiconductor devices makes it possible to integrate the deep submicron MOS transistors, resulting in the requirement of the shallow junction below 0.1 micrometer in 64M DRAM, 256M DRAM or next generation devices. The formation of a shallow junction is currently accomplished by the various methods developed, such as the method utilizing a sidewall spacer, ion implantation process, the semiconductor process without ion implantation process, or the silicide.
The LDD MOS transistor having the formed shallow junction by use of the sidewall spacer has the characteristics of the increased breakdown voltage and mitigated hot carrier effects.
The materials for making LDD MOS transistor has been adopted a high dielectric constant material such as the polysilicon or Si3N4 instead of SiO2, as the integrated density of the devices increases.
Recently, there is provided a method for fabricating LDD MOS transistor having the formed shallow junction by use of the sidewall spacer of in situ boron--doped polysilicon film or Boro Silicate Glass (BSG).
The P+ type source/drain area is formed using B+ or BF2+ as a doping source in case that P channel MOS transistor is made through the ion implant process.
However, it is difficult to form the shallow junction because of the tailing effect and large diffusion coefficient of Boron ion. There has been proposed the method for forming the P type source/drain of the shallow junction, comprising the steps of making the substrate amorphous by use of the big atoms such as Ga+, Ge+, S+, As+ or the like and implanting Boron ions at low energy level of about 10 KeV.
In addition, it was provided the method for forming the shallow junction depth below 1000 angstrom through the implantation at lower energy level of 200 keV.
But, there is problem of the leakage current due to the generated crystal defects after the formation of the junction, in the proposed technique for forming the shallow source/drain junction by use of the amorphous substrate.
Without implant process, the shallow junction formation technique enables to prevent the leakage current due to the crystal defects and one may be able to select one of various methods such as SOS(Spin-On Source), GILD(Gas Immersed Laser Doping), PILL(Plasma Immersion Ion Implantation), FIB(Focused Ion Beam), or methods utilizing a layer of BSG or TiB2.
Further, there is provided a method for forming the shallow junction below 500 angstrom by use of the silicide formed from CoSi2 and low energy.
For the reference to the shallow junction formation technique by use of CVD oxide layer doped with the impurities such as BSG or PSG(Phosphor Silicate Glass) without ion implant, it is seen from IEDM Tech, Dig., pp 897-900.
FIG. 1 is a sectional view of P channel MOS transistor formed using CVD oxide layer doped with impurities.
A thin insulative film and polysilicon film are deposit over a silicon substrate 11 and then those deposited films are patterned to form a gate insulating layer 12 and a gate 13.
A layer of BSG as the P doped CVD oxide layer is deposited on the whole surface of the resultant structure followed by etch back process to make spacer 14 on sidewall surface of the gate 13. Next, an annealing process of RTA(rapid thermal annealing) is carried out and boron is diffused into the silicon substrate 11 from the side wall spacer 14 of BSG film, thereby forming a highly doped shallow source/drain junction 15.
The heavy P implant is performed with a long range and followed by annealing step, so as to form the highly doped source/drain area 16 with deep junction. Of course, a layer of PSG can be used instead of a layer of BSG when making n type MOS transistor.
In case that p or n type MOS transistor is made using either a layer of BSG or PSG, a layer of BSG consisting of SiO2+B2O3 provides an effect of the reduced fusion temperature of oxide layer which leads to the improved planarization, but has no the gettering effect, whereas a layer of PSG consisting of SiO2+P2O5 provides the gettering of the metal ions such as Na+, but has the high fusion temperature characteristics about a layer of oxide.
Further, another problem resides in the exclusive use of BSG layer for p type MOS transistor and PSG for n type MOS transistor, respectively.